1. Field of the Invention
The present invention relates to an active matrix display. Such a display may be used, for example, for displaying images and graphical features such as icons in portable battery-operated equipment. Such a display may be sufficient on its own, for example as a reflective display, or may require other components, such as a backlight or a projection system, in order to form a complete display apparatus.
2. Description of the Related Art
FIG. 1 of the accompanying drawings illustrates a typical active matrix display comprising an active matrix 1 of N rows and M columns of picture elements (pixels) 2. Timing, control and data signals are supplied to a display controller 3, which supplies appropriate signals to a data line driver 4 and a scan line driver 5. The data and scan line drivers 4 and 5 provide the appropriate voltages to the electrodes of the pixels 2 via data lines 6 and scan lines 7. In a typical display of this type, each row of image data is supplied to the data line driver 4 and converted into the appropriate pixel voltages which are supplied via the data lines 6 to the columns of pixels. The scan line driver 5 supplies scan signals one at a time in sequence on the scan lines 7 to scan each row of pixel data into the appropriate row of pixels 2. The voltages supplied to the pixels are such as to cause the desired optical response of each pixel.
FIG. 2 of the accompanying drawings illustrates the arrangement of four pixels of the matrix 1. Each pixel comprises a thin film transistor (TFT) 10 which operates as a switch. The TFTs 10 may be implemented as amorphous silicon TFTs or low temperature poly-silicon TFTs, for example. The gate of each TFT 10 is connected to a scan line 7 whereas the source of each TFT 10 is connected to a data line 6. The drain of each TFT 10 is connected to a pixel electrode 11 and to a first electrode of a storage capacitor Cs, whose second electrode is connected to a common line 12 which is common to the second electrodes of the storage capacitors of all of the pixels in the display illustrated in FIG. 2.
The optical elements 13 of the display are illustrated as being liquid crystal elements but other types of element such as organic electroluminescent elements may also be used. The liquid crystal of each pixel is disposed between the pixel electrode 11 and a common electrode 14 with the common electrodes of all of the pixels generally being connected to a constant DC potential (Vcom). FIG. 3 of the accompanying drawings illustrates a typical optical response of a reflective liquid crystal pixel of the display of FIGS. 1 and 2 as normalised reflectance plotted against the voltage applied between the electrodes 11 and 14. The optical response is substantially symmetrical about zero volts and, in order to provide a grey-scale display element, the pixel electrode 11 and the storage capacitor Cs may be charged to any voltage from −4 volts to +4 volts with respect to Vcom.
In order to prevent degradation of the liquid crystal material by ionic transport mechanisms, the time-averaged voltage across the liquid crystal layer should be substantially zero. For a given optical state, this may be achieved by periodically reversing the polarity of the voltage across the liquid crystal layer of each pixel, for example each time the pixel is updated or refreshed. For example, in order to display a constant optical state of approximately 50% reflectance, the pixel electrode is alternately refreshed to +1.75V and −1.75V with respect to Vcom.
All of the pixels 2 of the active matrix 1 are refreshed at a frequency known as the frame rate. As mentioned hereinbefore, refreshing of each frame of image data is typically performed on a row-by-row basis. For each row of pixels, the data line driver 4 receives a row of image data to be displayed and charges the data lines 6 to the appropriate analog voltages. The scan line driver 5 activates a scan line such that all of the TFTs 10 in the matrix row whose gates are connected to the activated scan line are switched on. The TFTs 10 transfer charges from the data lines to the storage capacitors Cs until the voltage of each capacitor is the same as the data line to which it is connected. The scan line is then deactivated and the TFTs 10 of the row of pixels return to a high impedance state. This is repeated for each row of pixels.
FIG. 4 of the accompanying drawings illustrates typical timing signals in the display of FIG. 1. The display controller 3 receives VSYNC, HSYNC and DATA signals with each vertical synchronising signal indicating the transmission of a new frame of image data and each horizontal synchronising signal indicating the transmission of a row of data. The N scan lines 7 receive the scan line signals G1-GN as shown in FIG. 4. The frame rate is given by the frequency or repetition rate of the vertical synchronising signal VSYNC and the power consumption of the active matrix 1 is substantially proportional to the frame rate.
FIG. 5 of the accompanying drawings illustrates a typical general purpose display controller suitable for use as the controller shown at 3 in FIG. 1. The controller is formed as an integrated circuit for receiving digital display signals and comprises a timing generator for receiving display clock signals DCK, horizontal synchronising signals HSYNC and vertical synchronising signals VSYNC and for controlling timing of the controller 3. A matrix 21 is provided for converting luminance and chrominance signals Y, Cr, Cb to RGB format. The controller also has inputs for receiving RGB format signals, which bypass the matrix 21.
The image data signals are supplied to an on-screen display mixer 22 which mixes the image data signals with on-screen display signals stored in a frame buffer in the form of a static random access memory (SRAM) 23. The final image data for display are supplied to a gamma correction circuit 24 which compensates for any non-linear response of the display, such as the response illustrated in FIG. 3 of the accompanying drawings. The gamma correction circuit 24 has a picture adjust input which allows the colour, brightness and tint of the image to be adjusted.
The digital output from the circuit 24 is supplied to an output of the controller for use with displays requiring digital data. However, the controller 3 also comprises a digital/analog converter (DAC) 25 and an amplifier 26 for supplying image data signals in analog format.
If on-screen display data are required, such as icons, menus and graphical features, the appropriate image data are written into the memory 23. The memory 23 typically holds only one bit per pixel so as to allow binary (as opposed to grey-scale) on-screen data display. The data in the memory 23 overwrite the image data supplied to the controller 3 so as to make the on-screen display data visible over the arbitrary image data to be displayed.
Although such an arrangement is flexible and allows complex overlay data to be displayed, such an arrangement is excessively complex when the presentation of, for example, only a few simple icons is required. Further, because the on-screen data are mixed with the image data for the whole display, updating of the overlay image data necessitates refreshing of the whole display.